(1) Field of the Invention
This invention relates to a decoder circuit utilizing the Josephson device.
(2) Description of the Prior Art
The existing decoders of Josephson memory circuits are classified into several kinds, but each decoder is basically composed of a combination of current flip-flop circuits one of which is shown in FIG. 1. In the current flip-flop, when an input signal current S.sub.1 is applied to the Josephson junction J.sub.1 in the left side while a bias current I.sub.B flows through the Josephson junction, this junction momentarily acquires a voltage state and the bias current I.sub.B essentially flows through the junction J.sub.2 in the right side. When an input current S.sub.2 flows, on the contrary, to the junction J.sub.2 in the right side, the bias current I.sub.B essentially flows through the left side junction J.sub.1. In any case, the junctions J.sub.1, J.sub.2 are connected in parallel, and when the one is in the voltage state, the other is in the supercurrent state. Therefore, when one is returned to the supercurrent state, the current path is switched. A combination of such current flip-flops forms the so called tree decoder as shown in FIG. 2 which is demonstrated in the IEEE J. Solid State Circ., Vol. SC-13, No. 5, PP. 591-600, 1978 by W. H. Henkels and H. Zappe. The circuit shown in FIG. 2 is an example of the 8-bit address decoder, where a current flows in one of the address lines AL.sub.1 to AL.sub.8 according to the 3-bit input signals A.sub.1, A.sub.2, A.sub.3. For example, when the address bit A.sub.1 is 1, the junction J.sub.1 becomes ON (voltage state) and the current I.sub.B flows in the branch including the junction J.sub.2. When the address bit A.sub.2 is 0, the inverted bit A.sub.2 is 1 and therefore the junction J.sub.6 becomes ON, causing the current I.sub.B to flow into the branch including the junction J.sub.5. Moreover, when the address bit A.sub.3 is 1, the junction J.sub.11 becomes ON and the current flows in the address line AL.sub.6 including the junction J.sub.12 (AL.sub.6 is selected). The desired one address line among 2.sup.n lines can be selected in this way with an input signal of n-bits. The loop decoder is also proposed in the IEEE J. Solid State Circ. Vol. SC-14, No. 4, PP. 699-707, 1979 by S. Faris as another type of decoder circuit. These decoder circuits are all composed of combinations of current flip-flop circuits or modified circuits. But the current flip-flop has as a load the superconducting loop inductance from the point of view of the Josephson junction. For this reason, such a decoder circuit has the disadvantage that if the address lines AL.sub.1 to AL.sub.8 become long, a longer period is required for switching the branch circuit of the current I.sub.B. In practice, the switching period is on the order of nanosecond and the decoder circuit utilizing such current flip-flops cannot sufficiently utilize the high speed characteristic (several 10 PS) of the Josephson device.